diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
new file mode 100644
index 0000000..d180e04
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_EBC_H_
+#define _PPC4xx_EBC_H_
+
+/*
+ * Currently there are two register layout versions for the
+ * IBM EBC core used on 4xx PPC's:
+ */
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+    defined(CONFIG_405EP) || \
+    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define CONFIG_EBC_PPC4xx_IBM_VER1
+#endif
+
+/* Bank Configuration Register */
+#define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
+#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
+#define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
+#define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)
+#define EBC_BXCR_BS_4MB		PPC_REG_VAL(14, 0x2)
+#define EBC_BXCR_BS_8MB		PPC_REG_VAL(14, 0x3)
+#define EBC_BXCR_BS_16MB	PPC_REG_VAL(14, 0x4)
+#define EBC_BXCR_BS_32MB	PPC_REG_VAL(14, 0x5)
+#define EBC_BXCR_BS_64MB	PPC_REG_VAL(14, 0x6)
+#define EBC_BXCR_BS_128MB	PPC_REG_VAL(14, 0x7)
+#define EBC_BXCR_BU_MASK	PPC_REG_VAL(16, 0x3)
+#define	EBC_BXCR_BU_NONE	PPC_REG_VAL(16, 0x0)
+#define EBC_BXCR_BU_R		PPC_REG_VAL(16, 0x1)
+#define EBC_BXCR_BU_W		PPC_REG_VAL(16, 0x2)
+#define EBC_BXCR_BU_RW		PPC_REG_VAL(16, 0x3)
+#define EBC_BXCR_BW_MASK	PPC_REG_VAL(18, 0x3)
+#define EBC_BXCR_BW_8BIT	PPC_REG_VAL(18, 0x0)
+#define EBC_BXCR_BW_16BIT	PPC_REG_VAL(18, 0x1)
+#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
+#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x2)
+#else
+#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x3)
+#endif
+
+/* Bank Access Parameter Register */
+#define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
+#define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
+#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0xFF)
+#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, (static_cast(u32, n)) & 0x1F)
+#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0x7)
+#define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
+#define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
+#define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_BCT_2TRANS	PPC_REG_VAL(11, 0x0)
+#define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
+#define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
+#define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
+#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, (static_cast(u32, n)) & 0x3)
+#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, (static_cast(u32, n)) & 0x7)
+#define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
+#define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
+#define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)
+#define EBC_BXAP_SOR_NONDELAYED	PPC_REG_VAL(24, 0x1)
+#define EBC_BXAP_BEM_WRITEONLY	PPC_REG_VAL(25, 0x0)
+#define EBC_BXAP_BEM_RW		PPC_REG_VAL(25, 0x1)
+#define EBC_BXAP_PEN_DISABLED	PPC_REG_VAL(26, 0x0)
+#define EBC_BXAP_PEN_ENABLED	PPC_REG_VAL(26, 0x1)
+
+/* Common fields in EBC0_CFG register */
+#define EBC_CFG_PTD_MASK	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_PTD_ENABLE	PPC_REG_VAL(1, 0x0)
+#define EBC_CFG_PTD_DISABLE	PPC_REG_VAL(1, 0x1)
+#define EBC_CFG_RTC_MASK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_RTC_16PERCLK	PPC_REG_VAL(4, 0x0)
+#define EBC_CFG_RTC_32PERCLK	PPC_REG_VAL(4, 0x1)
+#define EBC_CFG_RTC_64PERCLK	PPC_REG_VAL(4, 0x2)
+#define EBC_CFG_RTC_128PERCLK	PPC_REG_VAL(4, 0x3)
+#define EBC_CFG_RTC_256PERCLK	PPC_REG_VAL(4, 0x4)
+#define EBC_CFG_RTC_512PERCLK	PPC_REG_VAL(4, 0x5)
+#define EBC_CFG_RTC_1024PERCLK	PPC_REG_VAL(4, 0x6)
+#define EBC_CFG_RTC_2048PERCLK	PPC_REG_VAL(4, 0x7)
+#define EBC_CFG_PME_MASK	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
+#define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
+#define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
+#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, (static_cast(u32, n)) & 0x1F)
+
+/* Now the two versions of the other bits */
+#if defined(CONFIG_EBC_PPC4xx_IBM_VER1)
+#define EBC_CFG_EBTC_MASK	PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_EBTC_HI		PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_EBTC_DRIVEN	PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_EMPH_MASK	PPC_REG_VAL(6, 0x3)
+#define EBC_CFG_EMPH_ENCODE(n)	PPC_REG_VAL(6, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_EMPL_MASK	PPC_REG_VAL(8, 0x3)
+#define EBC_CFG_EMPL_ENCODE(n)	PPC_REG_VAL(8, (static_cast(u32, n)) & 0x3)
+#define EBC_CFG_CSTC_MASK	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_CSTC_HI		PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_CSTC_DRIVEN	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_BPR_MASK	PPC_REG_VAL(11, 0x3)
+#define EBC_CFG_BPR_1DW		PPC_REG_VAL(11, 0x0)
+#define EBC_CFG_BPR_2DW		PPC_REG_VAL(11, 0x1)
+#define EBC_CFG_BPR_4DW		PPC_REG_VAL(11, 0x2)
+#define EBC_CFG_EMS_MASK	PPC_REG_VAL(13, 0x3)
+#define EBC_CFG_EMS_8BIT	PPC_REG_VAL(13, 0x0)
+#define EBC_CFG_EMS_16BIT	PPC_REG_VAL(13, 0x1)
+#define EBC_CFG_EMS_32BIT	PPC_REG_VAL(13, 0x2)
+#else
+#define EBC_CFG_LE_MASK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_LE_UNLOCK	PPC_REG_VAL(0, 0x0)
+#define EBC_CFG_LE_LOCK		PPC_REG_VAL(0, 0x1)
+#define EBC_CFG_ATC_MASK	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_ATC_HI		PPC_REG_VAL(5, 0x0)
+#define EBC_CFG_ATC_PREVIOUS	PPC_REG_VAL(5, 0x1)
+#define EBC_CFG_DTC_MASK	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_DTC_HI		PPC_REG_VAL(6, 0x0)
+#define EBC_CFG_DTC_PREVIOUS	PPC_REG_VAL(6, 0x1)
+#define EBC_CFG_CTC_MASK	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_CTC_HI		PPC_REG_VAL(7, 0x0)
+#define EBC_CFG_CTC_PREVIOUS	PPC_REG_VAL(7, 0x1)
+#define EBC_CFG_OEO_MASK	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_OEO_HI		PPC_REG_VAL(8, 0x0)
+#define EBC_CFG_OEO_PREVIOUS	PPC_REG_VAL(8, 0x1)
+#define EBC_CFG_EMC_MASK	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_EMC_NONDEFAULT	PPC_REG_VAL(9, 0x0)
+#define EBC_CFG_EMC_DEFAULT	PPC_REG_VAL(9, 0x1)
+#define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
+#define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
+#define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
+#define EBC_CFG_PR_64		PPC_REG_VAL(21, 0x2)
+#define EBC_CFG_PR_128		PPC_REG_VAL(21, 0x3)
+#endif
+
+#endif /* _PPC4xx_EBC_H_ */
diff --git a/include/ppc405.h b/include/ppc405.h
index 061ac70..fee4ee5 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -366,120 +366,6 @@
 #define UIC_EXT6      0x00000001      /* External  interrupt 6		    */
 #endif	/* defined(CONFIG_405EZ) */
 
-/******************************************************************************
- * External Bus Controller (EBC)
- *****************************************************************************/
-
-/* Bank Configuration Register */
-#define	EBC_BXCR_BAS_MASK	PPC_REG_VAL(11, 0xFFF)
-#define EBC_BXCR_BAS_ENCODE(n)	(((static_cast(unsigned long, n)) & \
-				  EBC_BXCR_BAS_MASK) << 0)
-#define EBC_BXCR_BS_MASK	PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BS_1MB		PPC_REG_VAL(14, 0x0)
-#define EBC_BXCR_BS_2MB		PPC_REG_VAL(14, 0x1)
-#define EBC_BXCR_BS_4MB		PPC_REG_VAL(14, 0x2)
-#define EBC_BXCR_BS_8MB		PPC_REG_VAL(14, 0x3)
-#define EBC_BXCR_BS_16MB	PPC_REG_VAL(14, 0x4)
-#define EBC_BXCR_BS_32MB	PPC_REG_VAL(14, 0x5)
-#define EBC_BXCR_BS_64MB	PPC_REG_VAL(14, 0x6)
-#define EBC_BXCR_BS_128MB	PPC_REG_VAL(14, 0x7)
-#define EBC_BXCR_BU_MASK	PPC_REG_VAL(16, 0x3)
-#define	EBC_BXCR_BU_NONE	PPC_REG_VAL(16, 0x0)
-#define EBC_BXCR_BU_R		PPC_REG_VAL(16, 0x1)
-#define EBC_BXCR_BU_W		PPC_REG_VAL(16, 0x2)
-#define EBC_BXCR_BU_RW		PPC_REG_VAL(16, 0x3)
-#define EBC_BXCR_BW_MASK	PPC_REG_VAL(18, 0x3)
-#define EBC_BXCR_BW_8BIT	PPC_REG_VAL(18, 0x0)
-#define EBC_BXCR_BW_16BIT	PPC_REG_VAL(18, 0x1)
-#define EBC_BXCR_BW_32BIT	PPC_REG_VAL(18, 0x3)
-
-/* Bank Access Parameter Register */
-#define EBC_BXAP_BME_ENABLED	PPC_REG_VAL(0, 0x1)
-#define EBC_BXAP_BME_DISABLED	PPC_REG_VAL(0, 0x0)
-#define EBC_BXAP_TWT_ENCODE(n)	PPC_REG_VAL(8, \
-					    (static_cast(unsigned long, n)) \
-					    & 0xFF)
-#define	EBC_BXAP_FWT_ENCODE(n)	PPC_REG_VAL(5, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x1F)
-#define	EBC_BXAP_BWT_ENCODE(n)	PPC_REG_VAL(8, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x7)
-#define EBC_BXAP_BCE_DISABLE	PPC_REG_VAL(9, 0x0)
-#define EBC_BXAP_BCE_ENABLE	PPC_REG_VAL(9, 0x1)
-#define EBC_BXAP_BCT_MASK	PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_BCT_2TRANS	PPC_REG_VAL(11, 0x0)
-#define EBC_BXAP_BCT_4TRANS	PPC_REG_VAL(11, 0x1)
-#define EBC_BXAP_BCT_8TRANS	PPC_REG_VAL(11, 0x2)
-#define EBC_BXAP_BCT_16TRANS	PPC_REG_VAL(11, 0x3)
-#define EBC_BXAP_CSN_ENCODE(n)	PPC_REG_VAL(13, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x3)
-#define EBC_BXAP_OEN_ENCODE(n)	PPC_REG_VAL(15, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x3)
-#define EBC_BXAP_WBN_ENCODE(n)	PPC_REG_VAL(17, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x3)
-#define EBC_BXAP_WBF_ENCODE(n)	PPC_REG_VAL(19, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x3)
-#define EBC_BXAP_TH_ENCODE(n)	PPC_REG_VAL(22, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x7)
-#define EBC_BXAP_RE_ENABLED	PPC_REG_VAL(23, 0x1)
-#define EBC_BXAP_RE_DISABLED	PPC_REG_VAL(23, 0x0)
-#define EBC_BXAP_SOR_DELAYED	PPC_REG_VAL(24, 0x0)
-#define EBC_BXAP_SOR_NONDELAYED	PPC_REG_VAL(24, 0x1)
-#define EBC_BXAP_BEM_WRITEONLY	PPC_REG_VAL(25, 0x0)
-#define EBC_BXAP_BEM_RW		PPC_REG_VAL(25, 0x1)
-#define EBC_BXAP_PEN_DISABLED	PPC_REG_VAL(26, 0x0)
-#define EBC_BXAP_PEN_ENABLED	PPC_REG_VAL(26, 0x1)
-
-/* Configuration Register */
-#define EBC_CFG_LE_MASK		PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_LE_UNLOCK	PPC_REG_VAL(0, 0x0)
-#define EBC_CFG_LE_LOCK		PPC_REG_VAL(0, 0x1)
-#define EBC_CFG_PTD_MASK	PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_PTD_ENABLE	PPC_REG_VAL(1, 0x0)
-#define EBC_CFG_PTD_DISABLE	PPC_REG_VAL(1, 0x1)
-#define EBC_CFG_RTC_MASK	PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_RTC_16PERCLK	PPC_REG_VAL(4, 0x0)
-#define EBC_CFG_RTC_32PERCLK	PPC_REG_VAL(4, 0x1)
-#define EBC_CFG_RTC_64PERCLK	PPC_REG_VAL(4, 0x2)
-#define EBC_CFG_RTC_128PERCLK	PPC_REG_VAL(4, 0x3)
-#define EBC_CFG_RTC_256PERCLK	PPC_REG_VAL(4, 0x4)
-#define EBC_CFG_RTC_512PERCLK	PPC_REG_VAL(4, 0x5)
-#define EBC_CFG_RTC_1024PERCLK	PPC_REG_VAL(4, 0x6)
-#define EBC_CFG_RTC_2048PERCLK	PPC_REG_VAL(4, 0x7)
-#define EBC_CFG_ATC_MASK	PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_ATC_HI		PPC_REG_VAL(5, 0x0)
-#define EBC_CFG_ATC_PREVIOUS	PPC_REG_VAL(5, 0x1)
-#define EBC_CFG_DTC_MASK	PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_DTC_HI		PPC_REG_VAL(6, 0x0)
-#define EBC_CFG_DTC_PREVIOUS	PPC_REG_VAL(6, 0x1)
-#define EBC_CFG_CTC_MASK	PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_CTC_HI		PPC_REG_VAL(7, 0x0)
-#define EBC_CFG_CTC_PREVIOUS	PPC_REG_VAL(7, 0x1)
-#define EBC_CFG_OEO_MASK	PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_OEO_DISABLE	PPC_REG_VAL(8, 0x0)
-#define EBC_CFG_OEO_ENABLE	PPC_REG_VAL(8, 0x1)
-#define EBC_CFG_EMC_MASK	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_EMC_NONDEFAULT	PPC_REG_VAL(9, 0x0)
-#define EBC_CFG_EMC_DEFAULT	PPC_REG_VAL(9, 0x1)
-#define EBC_CFG_PME_MASK	PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PME_DISABLE	PPC_REG_VAL(14, 0x0)
-#define EBC_CFG_PME_ENABLE	PPC_REG_VAL(14, 0x1)
-#define EBC_CFG_PMT_MASK	PPC_REG_VAL(19, 0x1F)
-#define EBC_CFG_PMT_ENCODE(n)	PPC_REG_VAL(19, \
-					    (static_cast(unsigned long, n)) \
-					    & 0x1F)
-#define EBC_CFG_PR_MASK		PPC_REG_VAL(21, 0x3)
-#define EBC_CFG_PR_16		PPC_REG_VAL(21, 0x0)
-#define EBC_CFG_PR_32		PPC_REG_VAL(21, 0x1)
-#define EBC_CFG_PR_64		PPC_REG_VAL(21, 0x2)
-#define EBC_CFG_PR_128		PPC_REG_VAL(21, 0x3)
-
 #ifndef CONFIG_405EP
 /******************************************************************************
  * Decompression Controller
diff --git a/include/ppc440.h b/include/ppc440.h
index fe988fb..f843792 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1756,93 +1756,6 @@
 #endif /* CONFIG_440SPE */
 
 /*-----------------------------------------------------------------------------+
-|  External Bus Controller Bit Settings
-+-----------------------------------------------------------------------------*/
-#define EBC_CFGADDR_MASK		0x0000003F
-
-#define EBC_BXCR_BAS_ENCODE(n)	((((unsigned long)(n))&0xFFF00000)<<0)
-#define EBC_BXCR_BS_MASK		0x000E0000
-#define EBC_BXCR_BS_1MB			0x00000000
-#define EBC_BXCR_BS_2MB			0x00020000
-#define EBC_BXCR_BS_4MB			0x00040000
-#define EBC_BXCR_BS_8MB			0x00060000
-#define EBC_BXCR_BS_16MB		0x00080000
-#define EBC_BXCR_BS_32MB		0x000A0000
-#define EBC_BXCR_BS_64MB		0x000C0000
-#define EBC_BXCR_BS_128MB		0x000E0000
-#define EBC_BXCR_BU_MASK		0x00018000
-#define EBC_BXCR_BU_R			0x00008000
-#define EBC_BXCR_BU_W			0x00010000
-#define EBC_BXCR_BU_RW			0x00018000
-#define EBC_BXCR_BW_MASK		0x00006000
-#define EBC_BXCR_BW_8BIT		0x00000000
-#define EBC_BXCR_BW_16BIT		0x00002000
-#define EBC_BXCR_BW_32BIT		0x00006000
-#define EBC_BXAP_BME_ENABLED		0x80000000
-#define EBC_BXAP_BME_DISABLED		0x00000000
-#define EBC_BXAP_TWT_ENCODE(n)		((((unsigned long)(n))&0xFF)<<23)
-#define EBC_BXAP_BCE_DISABLE		0x00000000
-#define EBC_BXAP_BCE_ENABLE		0x00400000
-#define EBC_BXAP_BCT_MASK		0x00300000
-#define EBC_BXAP_BCT_2TRANS		0x00000000
-#define EBC_BXAP_BCT_4TRANS		0x00100000
-#define EBC_BXAP_BCT_8TRANS		0x00200000
-#define EBC_BXAP_BCT_16TRANS		0x00300000
-#define EBC_BXAP_CSN_ENCODE(n)		((((unsigned long)(n))&0x3)<<18)
-#define EBC_BXAP_OEN_ENCODE(n)		((((unsigned long)(n))&0x3)<<16)
-#define EBC_BXAP_WBN_ENCODE(n)		((((unsigned long)(n))&0x3)<<14)
-#define EBC_BXAP_WBF_ENCODE(n)		((((unsigned long)(n))&0x3)<<12)
-#define EBC_BXAP_TH_ENCODE(n)		((((unsigned long)(n))&0x7)<<9)
-#define EBC_BXAP_RE_ENABLED		0x00000100
-#define EBC_BXAP_RE_DISABLED		0x00000000
-#define EBC_BXAP_SOR_DELAYED		0x00000000
-#define EBC_BXAP_SOR_NONDELAYED		0x00000080
-#define EBC_BXAP_BEM_WRITEONLY		0x00000000
-#define EBC_BXAP_BEM_RW			0x00000040
-#define EBC_BXAP_PEN_DISABLED		0x00000000
-
-#define EBC_CFG_LE_MASK			0x80000000
-#define EBC_CFG_LE_UNLOCK		0x00000000
-#define EBC_CFG_LE_LOCK			0x80000000
-#define EBC_CFG_PTD_MASK		0x40000000
-#define EBC_CFG_PTD_ENABLE		0x00000000
-#define EBC_CFG_PTD_DISABLE		0x40000000
-#define EBC_CFG_RTC_MASK		0x38000000
-#define EBC_CFG_RTC_16PERCLK		0x00000000
-#define EBC_CFG_RTC_32PERCLK		0x08000000
-#define EBC_CFG_RTC_64PERCLK		0x10000000
-#define EBC_CFG_RTC_128PERCLK		0x18000000
-#define EBC_CFG_RTC_256PERCLK		0x20000000
-#define EBC_CFG_RTC_512PERCLK		0x28000000
-#define EBC_CFG_RTC_1024PERCLK		0x30000000
-#define EBC_CFG_RTC_2048PERCLK		0x38000000
-#define EBC_CFG_ATC_MASK		0x04000000
-#define EBC_CFG_ATC_HI			0x00000000
-#define EBC_CFG_ATC_PREVIOUS		0x04000000
-#define EBC_CFG_DTC_MASK		0x02000000
-#define EBC_CFG_DTC_HI			0x00000000
-#define EBC_CFG_DTC_PREVIOUS		0x02000000
-#define EBC_CFG_CTC_MASK		0x01000000
-#define EBC_CFG_CTC_HI			0x00000000
-#define EBC_CFG_CTC_PREVIOUS		0x01000000
-#define EBC_CFG_OEO_MASK		0x00800000
-#define EBC_CFG_OEO_HI			0x00000000
-#define EBC_CFG_OEO_PREVIOUS		0x00800000
-#define EBC_CFG_EMC_MASK		0x00400000
-#define EBC_CFG_EMC_NONDEFAULT		0x00000000
-#define EBC_CFG_EMC_DEFAULT		0x00400000
-#define EBC_CFG_PME_MASK		0x00200000
-#define EBC_CFG_PME_DISABLE		0x00000000
-#define EBC_CFG_PME_ENABLE		0x00200000
-#define EBC_CFG_PMT_MASK		0x001F0000
-#define EBC_CFG_PMT_ENCODE(n)		((((unsigned long)(n))&0x1F)<<12)
-#define EBC_CFG_PR_MASK			0x0000C000
-#define EBC_CFG_PR_16			0x00000000
-#define EBC_CFG_PR_32			0x00004000
-#define EBC_CFG_PR_64			0x00008000
-#define EBC_CFG_PR_128			0x0000C000
-
-/*-----------------------------------------------------------------------------+
 |  SDR0 Bit Settings
 +-----------------------------------------------------------------------------*/
 #if defined(CONFIG_440SP)
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index 54897f7..ca0636c 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -53,6 +53,7 @@
 #endif
 
 #include <asm/ppc4xx-sdram.h>
+#include <asm/ppc4xx-ebc.h>
 
 /*
  * Macro for generating register field mnemonics